Scan driving device and method of driving the same

ABSTRACT

A scan driving device includes scan driving blocks, each including: a first node receiving a signal that is input to a first driving signal input terminal according to a clock signal input to a first clock signal input terminal; a second node receiving a second power source voltage according to the clock signal input to the first clock signal input terminal and a signal input to a second driving signal input terminal; a first transistor including a gate electrode connected to the second node and an electrode receiving an output control signal; a second transistor including a gate electrode connected to the first node and an electrode connected to a second clock signal input terminal; and a third transistor including a gate electrode connected to the second node, an electrode connected to a first power source voltage, and another electrode connected to the first node.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean PatentApplication No. 10-2011-0118368 filed in the Korean IntellectualProperty Office on Nov. 14, 2011, the entire contents of which areincorporated herein by reference.

BACKGROUND

1. Field

Embodiments relate to a scan driving device and a method of driving thesame. More particularly, embodiments relate to a scan driving device anda method of driving the same that may stably output a scan signal.

2. Description of the Related Art

In order to display an image, a flat panel display sequentially appliesa scan signal of a gate-on voltage to a plurality of scan lines andapplies a data signal corresponding to a scan signal of a gate-onvoltage to a plurality of data lines.

The above information disclosed in this Background section is only forenhancement of understanding and therefore it may contain informationthat does not form the prior art that is already known in this countryto a person of ordinary skill in the art.

SUMMARY

A scan driving device, including a plurality of sequentially arrangedscan driving blocks, each of the plurality of scan driving blocksincluding a first node to which a signal that is input to a firstdriving signal input terminal is transferred according to a clock signalthat is input to a first clock signal input terminal, a second node towhich a second power source voltage is transferred according to theclock signal that is input to the first clock signal input terminal anda signal that is input to a second driving signal input terminal, afirst transistor including a gate electrode that is connected to thesecond node and an electrode to which an output control signal is input,a second transistor including a gate electrode that is connected to thefirst node and an electrode that is connected to a second clock signalinput terminal, a contact point to which another electrode of the firsttransistor and another electrode of the second transistor are connectedbeing an output terminal, and a third transistor including a gateelectrode that is connected to the second node, an electrode that isconnected to a first power source voltage, and another electrode that isconnected to the first node.

Each of the plurality of scan driving blocks may further include afourth transistor including a gate electrode that is connected to thefirst clock signal input terminal, an electrode that is connected to thefirst clock signal input terminal, and another electrode that isconnected to the first node.

Each of the plurality of scan driving blocks may further include a fifthtransistor including a gate electrode that is connected to the firstdriving signal input terminal and an electrode that is connected to thefirst power source voltage, and a sixth transistor including a gateelectrode that is connected to the first clock signal input terminal, anelectrode that is connected to another electrode of the fifthtransistor, and another electrode that is connected to the second node.

Each of the plurality of scan driving blocks may further include aseventh transistor including a gate electrode that is connected to thesecond driving signal input terminal and an electrode that is connectedto the second power source voltage, and an eighth transistor including agate electrode that is connected to the first clock signal inputterminal, an electrode that is connected to another electrode of theseventh transistor, and another electrode that is connected to thesecond node.

Each of the plurality of scan driving blocks may further include a firstcapacitor including an electrode that is connected to the first node andanother electrode that is connected to the output terminal.

Each of the plurality of scan driving blocks may further include asecond capacitor including an electrode to which the output controlsignal is input and another electrode that is connected to the secondnode.

A first clock signal may be input to a first clock signal input terminalof a plurality of first scan driving blocks of the plurality of scandriving blocks, and a second clock signal may be input to a second clocksignal input terminal thereof, and the second clock signal may be inputto a first clock signal input terminal of a remaining plurality ofsecond scan driving blocks of the plurality of scan driving blocks, andthe first clock signal may be input to a second clock signal inputterminal thereof.

The second clock signal may be a signal that is shifted by duty of thefirst clock signal.

A scan signal of a previously arranged second scan driving block may beinput to the first driving signal input terminal of a subsequentlyarranged first scan driving block, and a scan signal of a subsequentlyarranged second scan driving block may be input to a second drivingsignal input terminal of a previously arranged first scan driving block.

A scan signal of the previously arranged first scan driving block may beinput to the first driving signal input terminal of the subsequentlyarranged second scan driving block, and a scan signal of thesubsequently arranged first scan driving block may be input to the firstdriving signal input terminal of the previously arranged second scandriving block.

A first clock signal may be input to a first clock signal input terminalof a first scan driving block of one of the plurality of scan drivingblocks, and a third clock signal that is shifted by duty of the firstclock signal may be input to the second clock signal input terminal ofthe first scan driving block, and a second clock signal that is shiftedby ½ duty of the first clock signal may be input to a first clock signalinput terminal of a second scan driving block that is arranged after thefirst scan driving block, and a fourth clock signal that is shifted by ½duty of the third clock signal may be input to the second clock signalinput terminal of the second scan driving block.

A scan signal of a previously arranged scan driving block may be inputto the first driving signal input terminal of the first scan drivingblock, and a scan signal of a scan driving block that is arranged afterthe second scan driving block may be input to the second driving signalinput terminal of the first scan driving block.

A scan signal of the first scan driving block may be input to the firstdriving signal input terminal of the second scan driving block.

A first clock signal may be input to a first clock signal input terminalof a first scan driving block of one of the plurality of scan drivingblocks, and a second clock signal that is shifted by ½ duty of the firstclock signal may be input to the second clock signal input terminal ofthe first scan driving block, the second clock signal may be input tothe first clock signal input terminal of a second scan driving blockthat is arranged after the first scan driving block, and a third clocksignal that is shifted by ½ duty of the second clock signal may be inputto the second clock signal input terminal of the second scan drivingblock, and the third clock signal may be input to a first clock signalinput terminal of a third scan driving block that is arranged after thesecond scan driving block, and a fourth clock signal that is shifted by½ duty of the third clock signal may be input to the second clock signalinput terminal of the third scan driving block.

A scan signal of a previously arranged scan driving block may be inputto the first driving signal input terminal of the first scan drivingblock, and a scan signal of the third scan driving block may be input tothe second driving signal input terminal of the first scan drivingblock.

A scan signal of the first scan driving block may be input to a firstdriving signal input terminal of the second scan driving block.

Another embodiment is directed to a scan driving device, including afirst node to which a signal that is input to a first driving signalinput terminal is transferred according to a clock signal that is inputto a first clock signal input terminal, a second node to which a signalthat is input to a second driving signal input terminal is transferredaccording to the clock signal that is input to the first clock signalinput terminal and the signal that is input to the second driving signalinput terminal, a first transistor including a gate electrode that isconnected to the second node and an electrode to which an output controlsignal is input, a second transistor including a gate electrode that isconnected to the first node and an electrode that is connected to asecond clock signal input terminal, a contact point to which anotherelectrode of the first transistor and another electrode of the secondtransistor are connected being an output terminal, and a thirdtransistor including a gate electrode that is connected to the secondnode, an electrode that is connected to a first power source voltage,and another electrode that is connected to the first node.

Another embodiment is directed to a scan driving device, including afirst node to which a signal that is input to a first driving signalinput terminal is transferred according to a clock signal that is inputto a first clock signal input terminal, a second node to which a secondpower source voltage is transferred according to the clock signal thatis input to the first clock signal input terminal and a signal that isinput to a second driving signal input terminal, a first transistorincluding a gate electrode that is connected to the second node and anelectrode to which an output control signal is input, a secondtransistor including a gate electrode that is connected to the firstnode and an electrode that is connected to a second clock signal inputterminal, a contact point to which another electrode of the firsttransistor and another electrode of the second transistor are connectedbeing an output terminal, and a third transistor including a gateelectrode that is connected to the second node, an electrode that isconnected to the second clock signal input terminal, and anotherelectrode that is connected to the first node.

Another embodiment is directed to a method of driving a scan drivingdevice that includes a plurality of scan driving blocks each including afirst node, a second node, a first transistor that has a gate electrodeconnected to the second node and that transfers an output control signalto an output terminal, a second transistor that has a gate electrodeconnected to the first node and that transfers a second clock signal tothe output terminal, a third transistor that has a gate electrodeconnected to the second node and that transfers a gate-off voltage tothe first node, and a capacitor that is connected to the first node andthe output terminal, the method including changing a voltage of thesecond node by the output control signal of a gate-on voltage, turningon the first transistor by a voltage change of the second node andoutputting the output control signal of the gate-on voltage as a scansignal to the output terminal, and turning on the third transistor by avoltage change of the second node and turning off the second transistorby a first power source voltage having the gate-off voltage.

The changing of a voltage of the second node and the outputting of theoutput control signal of the gate-on voltage may simultaneously occur inthe plurality of scan driving blocks.

The method may further include applying a scan signal of a gate-onvoltage that is output by a previously arranged scan driving block ofthe plurality of scan driving blocks according to the second clocksignal to the first node, turning on the second transistor by a gate-onvoltage of the first node and outputting the second clock signal of agate-off voltage as a scan signal to the output terminal, and chargingthe capacitor with a gate-on voltage of the first node and a gate-offvoltage of the output terminal.

The second clock signal may be a signal that is shifted by duty of thefirst clock signal.

The second clock signal may be a signal that is shifted by ½ duty of thefirst clock signal.

The method may further include changing the first clock signal to agate-on voltage, turning on the second transistor by boot strap throughthe capacitor, and outputting the second clock signal of the gate-onvoltage as the scan signal to the output terminal.

The method may further include applying a gate-on voltage to the secondnode by the second clock signal and a scan signal of a gate-on voltageof a subsequently arranged scan driving block of the plurality of scandriving blocks, turning on the first transistor by a gate-on voltage ofthe second node and outputting an output control signal of a gate-offvoltage as the scan signal to the output terminal, and transferring agate-off voltage to the first node by turning on the third transistor bya gate-on voltage of the second node and turning off the secondtransistor by a gate-off voltage of the first node.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a display device according to anexample embodiment.

FIG. 2 is a diagram illustrating a driving operation of a simultaneouslight emitting method of a display device according to an exampleembodiment.

FIG. 3 is a block diagram illustrating a configuration of a scan drivingdevice according to an example embodiment.

FIG. 4 is a circuit diagram illustrating an example embodiment of a scandriving block that is included in the scan driving device of FIG. 3.

FIG. 5 is a timing diagram illustrating a method of driving the scandriving device of FIG. 3.

FIG. 6 is a block diagram illustrating a configuration of a scan drivingdevice according to another example embodiment.

FIG. 7 is a timing diagram illustrating a method of driving the scandriving device of FIG. 6.

FIG. 8 is a block diagram illustrating a configuration of a scan drivingdevice according to another example embodiment.

FIG. 9 is a timing diagram illustrating a method of driving the scandriving device of FIG. 8.

FIG. 10 is a circuit diagram illustrating another example embodiment ofa scan driving block that is included in one scan driving device ofFIGS. 3, 6, and 8.

FIG. 11 is a circuit diagram illustrating another example embodiment ofa scan driving block that is included in one scan driving device ofFIGS. 3, 6, and 8.

DETAILED DESCRIPTION

Embodiments will be described more fully hereinafter with reference tothe accompanying drawings, in which example embodiments are shown. Asthose skilled in the art would realize, the described embodiments may bemodified in various different ways, all without departing from thespirit or scope of the disclosure.

Further, like reference numerals designate like elements in severalexample embodiments and are representatively described in a firstexample embodiment and elements different from those of the firstexample embodiment will be described in other example embodiments.

The drawings and description are to be regarded as illustrative innature and not restrictive. Like reference numerals designate likeelements throughout the specification.

Throughout this specification and the claims that follow, when it isdescribed that an element is “coupled” to another element, the elementmay be “directly coupled” to the other element or “electrically coupled”to the other element through a third element. In addition, unlessexplicitly described to the contrary, the word “comprise” and variationssuch as “comprises” or “comprising”, will be understood to imply theinclusion of stated elements but not the exclusion of any otherelements.

FIG. 1 is a block diagram illustrating a display device according to anexample embodiment.

In the example embodiment shown in FIG. 1, the display device includes asignal controller 100, a scan driving device 200, a data driver 300, anda display unit 500.

The signal controller 100 receives video signals R, G, and B that areinput from an external device and an input control signal that controlsthe display of the video signals R, G, and B. The video signals R, G,and B include luminance information of each pixel PX, and luminance hasgrays of the given number, for example, 1024 (=2¹⁰), 256 (=2⁸), or 64(=2⁶). The input control signal includes, for example, a verticalsynchronization signal Vsync, a horizontal synchronization signal Hsync,a main clock MCLK, and a data enable signal DE.

The signal controller 100 appropriately processes input video signals R,G, and B to correspond to an operation condition of the display unit 500and the data driver 300 based on the input video signals R, G, and B andthe input control signal and generates a scan control signal CONT1, adata control signal CONT2, and an image data signal DAT. The signalcontroller 100 transfers the scan control signal CONT1 to the scandriving device 200. The signal controller 100 transfers the data controlsignal CONT2 and the image data signal DAT to the data driver 300.

The display unit 500 includes a plurality of pixels PX that areconnected to a plurality of scan lines S1-Sn, a plurality of data linesD1-Dm, and a plurality of signal lines S1-Sn and D1-Dm to be arranged inan approximately matrix form. The plurality of scan lines S1-Sn areextended in an approximately row direction and are almost parallel toeach other. The plurality of data lines D1-Dm are extended in anapproximately column direction and are almost parallel to each other.The plurality of pixels PX of the display unit 500 receive a first powersource voltage VGH and a second power source voltage VGL from theoutside.

The scan driving device 200 is connected to the plurality of scan linesS1-Sn and applies a scan signal that is formed with a combination of agate-on voltage Von that turns on and a gate-off voltage Voff that turnsoff application of a data signal to the pixel PX according to the scancontrol signal CONT1 to the plurality of scan lines S1-Sn.

The scan control signal CONT1 includes a scan start signal SSP, a clocksignal CLK, and an output control signal GCK. The scan start signal SSPgenerates a first scan signal for displaying an image of a frame. Theclock signal CLK is a synchronization signal for sequentially applying ascan signal to the plurality of scan lines S1-Sn. The output controlsignal GCK is a signal that controls a scan signal to apply in a bundleto the plurality of scan lines S1-Sn.

The data driver 300 is connected to the plurality of data lines D1-Dmand selects a gray voltage according to an image data signal DAT. Thedata driver 300 applies a gray voltage that is selected according to thedata control signal CONT2 as a data signal to the plurality of datalines D1-Dm.

Each of the above-described driving devices 100, 200, and 300 is mountedat the outside of a pixel area in a form of at least one integratedcircuit chip, is mounted on a flexible printing circuit film, isattached to the display unit 500 in a form of a tape carrier package(TCP), is mounted on a separate printed circuit board, or is integratedat the outside of a pixel area together with the signal lines S1-Sn andD1-Dm.

The display device according to the present embodiment may be drivenwith a simultaneous light emitting method that uses a frame including ascan period in which a data signal is transferred and written to each ofa plurality of pixels PX and a light emitting period that emits lightaccording to a data signal in which each of a plurality of pixels PX iswritten.

FIG. 2 is a diagram illustrating a driving operation of a simultaneouslight emitting method of a display device according to an exampleembodiment.

In the example embodiment shown in FIG. 2, it is assumed that a displaydevice according to the present embodiment is an organic light emittingdiode (OLED) display using an OLED. However, the present embodiment isnot limited thereto and may be applied to various flat panel displays.

A method of driving the display device includes a reset step a thatresets a driving voltage of an OLED of a pixel, a threshold voltagecompensation step b that compensates a threshold voltage of a drivingtransistor of a pixel, a scan step c that transfers a data signal toeach of a plurality of pixels, and a light emitting step d in which aplurality of pixels emit light to correspond to a transferred datasignal.

In the example embodiment shown in FIG. 2, the scan step c sequentiallyperforms on each scan line basis, but the reset step a, the thresholdvoltage compensation step b, and the light emitting step d aresimultaneously performed in a bundle in the entire display unit 500.

Here, the scan driving device 200 of the display device according to thepresent embodiment sequentially applies a scan signal of a gate-onvoltage Von to the plurality of scan lines S1-Sn at the scan step c andsimultaneously applies a scan signal of a gate-on voltage Von to theplurality of scan lines S1-Sn at the reset step a and the thresholdvoltage compensation step b. Thus, the scan driving device 200 performssequential application and simultaneous application of a scan signalaccording to a driving step of the display device.

FIG. 3 is a block diagram illustrating a configuration of a scan drivingdevice according to an example embodiment.

In the example embodiment shown in FIG. 3, the scan driving deviceincludes a plurality of sequentially arranged scan driving blocks 210_1,210_2, 210_3, 210_4, . . . . The scan driving blocks 210_1, 210_2,210_3, 210_4, . . . receive an input signal and generate scan signalsS[1], S[2], S[3], S[4], . . . that are transferred to the plurality ofscan lines S1-Sn, respectively.

Each of the plurality of scan driving blocks 210_1, 210_2, 210_3, 210_4,. . . includes a first clock signal input terminal CK1, a second clocksignal input terminal CK2, an output control signal input terminal GK, afirst driving signal input terminal Input1, a second driving signalinput terminal Input2, and an output terminal OUT.

A first clock signal CLK1 is input to a first clock signal inputterminal CK1 of odd numbered scan driving blocks 210_1, 210_3, . . . ofthe plurality of scan driving blocks 210_1, 210_2, 210_3, 210_4, . . . ,and a second clock signal CLK2 is input to a second clock signal inputterminal CK2, thereof. A second clock signal CLK2 is input to a firstclock signal input terminal CK1 of even numbered scan driving blocks210_2, 210_4, . . . of the plurality of scan driving blocks 210_1,210_2, 210_3, 210_4, . . . , and a first clock signal CLK1 is input to asecond clock signal input terminal CK2 thereof.

An output control signal GCK is input to an output control signal inputterminal GK of the plurality of scan driving blocks 210_1, 210_2, 210_3,210_4, . . . .

A scan signal of a previously arranged scan driving block is input to afirst driving signal input terminal Input1 of the plurality of scandriving blocks 210_1, 210_2, 210_3, 210_4, . . . , and a scan signal ofa subsequently arranged scan driving block is input to a second drivingsignal input terminal Input2 thereof. Thus, a scan signal of previouslyarranged even numbered scan driving blocks is input to a first drivingsignal input terminal Input1 of odd numbered scan driving blocks, and ascan signal of subsequently arranged even numbered scan driving blocksis input to a second driving signal input terminal Input2 of oddnumbered scan driving blocks. A scan signal of previously arranged oddnumbered scan driving blocks is input to a first driving signal inputterminal Input1 of even numbered scan driving blocks, and a scan signalof subsequently arranged odd numbered scan driving blocks is input to asecond driving signal input terminal Input2 of even numbered scandriving blocks.

In an implementation, when the plurality of scan driving blocks 210_1,210_2, 210_3, 210_4, . . . sequentially output a scan signal, a scansignal S[k−1] of a (K−1)st scan driving block 210_k−1 is input to afirst driving signal input terminal Input1 of a k-th scan driving block210_k, and a scan signal S[k+1] of a (K+1)st scan driving block 210_k+1is input to a second driving signal input terminal Input2 thereof. Inthis case, a scan start signal SSP is input to a first driving signalinput terminal Input1 of a first scan driving block 210_1.

Each of the scan driving blocks 210_1, 210_2, 210_3, 210_4, . . .outputs scan signals S[1], S[2], S[3], S[4], . . . that are generatedaccording to a signal that is input to the first clock signal inputterminal CK1, the second clock signal input terminal CK2, the outputcontrol signal input terminal GK, the first driving signal inputterminal Input1, and the second driving signal input terminal Input2 tothe output terminal OUT.

The first scan driving block 210_1 transfers a scan signal S[1] that isgenerated by receiving a scan start signal SSP to a first scan line S1and a first driving signal input terminal Input1 of a second scandriving block 210_2. A k-th arranged scan driving block 210_k outputs ascan signal S[k] that is generated by receiving a scan signal S[k−1]that is output from a (K−1)st arranged scan driving block 210_k−1(1≦k<=n).

FIG. 4 is a circuit diagram illustrating an example embodiment of a scandriving block that is included in the scan driving device of FIG. 3.

In the example embodiment shown in FIG. 4, the scan driving blockincludes a plurality of transistors M11, M12, M13, M14, M15, M16, M17,and M18 and a plurality of capacitors C11 and C12.

A first transistor M11 includes a gate electrode that is connected to asecond node N12, one electrode that is connected to an output controlsignal input terminal GK, and another electrode that is connected to anoutput terminal OUT.

A second transistor M12 includes a gate electrode that is connected to afirst node N11, one electrode that is connected to a second clock signalinput terminal CK2, and another electrode that is connected to theoutput terminal OUT. A contact point to which the other electrode of thefirst transistor M11 and the other electrode of the second transistorM12 are connected is the output terminal OUT.

A third transistor M13 includes a gate electrode that is connected to afirst clock signal input terminal CK1, one electrode that is connectedto a first driving signal input terminal Input1, and another electrodethat is connected to the first node N11.

A fourth transistor M14 includes a gate electrode that is connected tothe first clock signal input terminal CK1, one electrode that isconnected to another electrode of a seventh transistor M17, and anotherelectrode that is connected to the second node N12.

A fifth transistor M15 includes a gate electrode that is connected tothe first driving signal input terminal Input1, one electrode that isconnected to a first power source voltage VGH, and another electrodethat is connected to a sixth transistor M16.

The sixth transistor M16 includes a gate electrode that is connected tothe first clock signal input terminal CK1, one electrode that isconnected to the other electrode of the fifth transistor M15, andanother electrode that is connected to the second node N12.

The seventh transistor M17 includes a gate electrode that is connectedto a second driving signal input terminal Input2, one electrode that isconnected to a second power source voltage VGL, and another electrodethat is connected to one electrode of the fourth transistor M14.

An eighth transistor M18 includes a gate electrode that is connected tothe second node N12, one electrode that is connected to the first powersource voltage VGH, and another electrode that is connected to the firstnode N11.

A first capacitor C11 includes one electrode that is connected to thefirst node N11 and another electrode that is connected to the outputterminal OUT. A second capacitor C12 includes one electrode that isconnected to the output control signal input terminal GK and anotherelectrode that is connected to the second node N12.

The first power source voltage VGH has a voltage of a logic high level,and the second power source voltage VGL has a voltage of a logic lowlevel.

The plurality of transistors M11, M12, M13, M14, M15, M16, M17, and M18are a p-channel field effect transistor. A gate-on voltage that turns onthe plurality of transistors M11, M12, M13, M14, M15, M16, M17, and M18is a voltage of a logic low level, and a gate-off voltage that turns offthe plurality of transistors M11, M12, M13, M14, M15, M16, M17, and M18is a voltage of a logic high level.

FIG. 5 is a timing diagram illustrating a method of driving the scandriving device of FIG. 3.

In the example embodiment shown in FIGS. 3 and 5, the scan drivingdevice simultaneously outputs a scan signal of a gate-on voltage to aplurality of scan lines S1-Sn at a reset step a and a threshold voltagecompensation step b and sequentially outputs a scan signal of a gate-onvoltage to a plurality of scan lines S1-Sn at a scan step c.

A segment t11-t12 is one segment of a reset step a and a thresholdvoltage compensation step b in which a scan signal of a gate-on voltageis simultaneously output to a plurality of scan lines S1-Sn. At thesegment t11-t12, an output control signal GCK is applied as a voltage ofa logic low level, and a scan start signal SSP, a first clock signalCLK1, and a second clock signal CLK2 are applied as a voltage of a logichigh level.

The first clock signal CLK1 or the second clock signal CLK2 of a logichigh level is applied through the first clock signal input terminal CLK1of the plurality of scan driving blocks 210_1, 210_2, 210_3, 210_4,. . .. The third transistor M13, the fourth transistor M14, and the sixthtransistor M16 are turned off. Because the third transistor M13, thefourth transistor M14, and the sixth transistor M16 are turned off, thefirst node N11 and the second node N12 are in a floating state.

At a time point t11, because a voltage of the output control signal GCKis lowered from a logic high level to a logic low level, a voltage ofthe second node N12 of a floating state is lowered to a logic low levelby coupling according to a voltage change of the output control signalGCK. Accordingly, the first transistor M11 and the eighth transistor M18are turned on. The first power source voltage VGH is transferred to thefirst node N11 through the turned-on eighth transistor M18, and thesecond transistor M12 is turned off. The output control signal GCK of alogic low level is transferred to the output terminal OUT through theturned-on first transistor M11.

In this way, the plurality of scan driving blocks 210_1, 210_2, 210_3,210_4, . . . simultaneously output scan signals S[1], S[2], S[3], S[4],. . . of a logic low level.

Segments after a segment t13 are segments of a scan step c in which ascan signal of a gate-on voltage is sequentially output to the pluralityof scan lines S1-Sn. At segments after the segment t13, the outputcontrol signal GCK is applied as a voltage of a logic high level.

At a segment t13-t14, the scan start signal SSP is applied as a voltageof a logic low level. A voltage of the first clock signal CLK1 isrepeatedly changed to a logic low level and a logic high level in a unitof 1 horizontal cycle (1H, a cycle of a horizontal synchronizationsignal) Hsync from a segment t13-t14. A voltage of the second clocksignal CLK2 is repeatedly changed to a logic low level and a logic highlevel in a unit of 1 horizontal cycle 1H from a segment t14-t15. Thus,the second clock signal CLK2 is a signal in which the first clock signalCLK1 is shifted by duty of the first scan clock signal CLK1. Duty of aclock signal is a segment in which a voltage that turns on a transistorthat is included in a scan driving block is applied.

At the segment t13-t14, a scan start signal SSP of a logic low level isapplied to a first driving signal input terminal Input1 of a first scandriving block 210_1, and a first clock signal CLK1 of a logic low levelis applied to a first clock signal input terminal CK1. The thirdtransistor M13, the fourth transistor M14, the fifth transistor M15, andthe sixth transistor M16 are turned on. A voltage of a logic low levelis transferred to the first node N11, and a voltage of a logic highlevel is transferred to the second node N12. The first transistor M11 isturned off, and the second transistor M12 is turned on. A voltage of alogic high level is transferred to the output terminal OUT through theturned-on second transistor M12. The first capacitor C11 is charged by avoltage difference between a voltage of a logic low level of the firstnode N11 and a voltage of a logic high level of the output terminal OUT.

At a segment t14-t15, a first clock signal CLK1 of a logic high level isapplied to the first clock signal input terminal CLK1 of the first scandriving block 210_1, and a second clock signal CLK2 of a logic low levelis applied to the second clock signal input terminal CK2. The thirdtransistor M13, the fourth transistor M14, and the sixth transistor M16are turned off and thus the first node N11 and the second node N12 arein a floating state. A voltage of the second node N12 sustains a logichigh level. The second transistor M12 is completely turned on by bootstrap through the first capacitor C11. A voltage of a logic low level istransferred to the output terminal OUT through the turned-on secondtransistor M12. Accordingly, the first scan driving block 210_1 outputsa scan signal S[1] of a logic low level.

At a segment t14-t15, a scan signal S[1] of a logic low level of thefirst scan driving block 210_1 is applied to a first driving signalinput terminal Input1 of a second scan driving block 210_2. A secondclock signal CLK2 of a logic low level is applied to a first clocksignal input terminal CK1 of the second scan driving block 210_2, andthe first clock signal CLK1 of a logic high level is applied to thesecond clock signal input terminal CK2. The second scan driving block210_2 operates like operation at a segment t14-t15 of the first scandriving block 210_1 and thus charges the first capacitor C11 by avoltage difference between a voltage of a logic low level of the firstnode N11 and a voltage of a logic high level of the output terminal OUT.

At a segment t15-t16, a second clock signal CLK2 of a logic high levelis applied to the first clock signal input terminal CK1 of the secondscan driving block 210_2, and a first clock signal CLK1 of a logic lowlevel is applied to the second clock signal input terminal CK2. Thesecond scan driving block 210_2 operates like operation at a segmentt14-t15 of the first scan driving block 210_1 and thus outputs a scansignal S[2] of a logic low level.

At the segment t15-t16, the scan signal S[2] of a logic low level of thesecond scan driving block 210_2 is transferred to a second drivingsignal input terminal Input2 of the first scan driving block 210_1. Afourth transistor M14 of the first scan driving block 210_1 is turned onby the first clock signal CLK1 of a logic low level, and a seventhtransistor M17 is turned on by the scan signal S[2] of the second scandriving block 210_2 of a logic low level. A voltage of a logic low levelof the second power source voltage VGL is transferred to the second nodeN12 of the first scan driving block 210_1. The first transistor M11 andthe eighth transistor M18 are turned on. A voltage of a logic high levelis transferred to the output terminal OUT through the turned-on firsttransistor M11. The first power source voltage VGH is transferred to thefirst node N11 through the turned-on eighth transistor M18.

In this way, after a scan signal of a logic low level is output, byturning on the eighth transistor M18, the first power source voltage VGHis transferred to the first node N11, whereby the scan signal S[1] ofthe first scan driving block 210_1 may be prevented from being shaken bya clock signal that is applied to the second clock signal input terminalCK2.

By the above-described method, the plurality of scan driving blocks210_1, 210_2, 210_3, 210_4, . . . sequentially output scan signals S[1],S[2], S[3], S[4], . . . of a logic low level.

After the scan driving block outputs a scan signal of a logic low level,when a voltage of a logic high level is not transferred to the firstnode N11, a voltage of the first node N11 may be shaken by a voltagechange of a clock signal that is input to the second clock signal inputterminal CK2. A voltage of the first node N11 may be shaken by couplingof the first node N11 and the output terminal OUT and thus an outputsignal of the output terminal OUT may be shaken.

However, after the scan driving block outputs a scan signal of a logiclow level, by turning on the eighth transistor using a scan signal of anext scan driving block, the scan driving device transfers a voltage ofa logic high level to the first node N11 and thus an output signal ofthe scan driving block may be prevented from being shaken.

FIG. 6 is a block diagram illustrating a configuration of a scan drivingdevice according to another example embodiment.

In the example embodiment shown in FIG. 6, the scan driving deviceincludes a sequentially arranged plurality of scan driving blocks 220_1,220_2, 220_3, 220_4, . . . . Each of scan driving blocks 220_1, 220_2,220_3, 220_4, . . . may be formed like the scan driving blocks of FIG.4.

A first clock signal CLK1 is input to a first clock signal inputterminal CK1 of a first scan driving block 220_1 of the plurality ofscan driving blocks 220_1, 220_2, 220_3, 220_4, . . . , and a thirdclock signal CLK3 is input to a second clock signal input terminal CK2thereof. A second clock signal CLK2 is input to a first clock signalinput terminal CK1 of a second scan driving block 220_2, and a fourthclock signal CLK4 is input to a second clock signal input terminal CK2thereof. A third clock signal CLK3 is input to a first clock signalinput terminal CK1 of a third scan driving block 220_3, and a first scanclock signal CLK1 is input to a second clock signal input terminal CK2thereof. A fourth scan driving block 220_4 is input to a first clocksignal input terminal CK1 of a fourth clock signal CLK4, and a secondclock signal CLK2 is input to a second clock signal input terminal CK2thereof.

The second clock signal CLK2 is a signal in which the first clock signalCLK1 is shifted by ½ duty of the first clock signal CLK1, a third clocksignal CLK3 is a signal in which the second clock signal CLK2 is shiftedby ½ duty of the second clock signal CLK2, and a fourth clock signalCLK4 is a signal in which the third clock signal CLK3 is shifted by ½duty of the third clock signal CLK3.

In this way, a clock signal that is shifted by a duty of a clock signalthat is input to the first clock signal input terminal CK1 is input tothe second clock signal input terminal CK2 of a first scan driving blockof one of the plurality of scan driving blocks 220_1, 220_2, 220_3,220_4, . . . . A clock signal that is shifted by ½ duty of a clocksignal that is input to the first clock signal input terminal CK1 of afirst scan driving block is input to the first clock signal inputterminal CK1 of a second scan driving block that is arranged after thefirst scan driving block. A clock signal that is shifted by ½ duty of aclock signal that is input to the second clock signal input terminal CK2of the first scan driving block is input to a second clock signal inputterminal CK2 of the second scan driving block.

An output control signal GCK is input to an output control signal inputterminal GK of the plurality of scan driving blocks 220_1, 220_2, 220_3,220_4, . . . .

When the plurality of scan driving blocks 220_1, 220_2, 220_3, 220_4, .. . sequentially output a scan signal, a scan signal S[k−1] of a (K−1)stscan driving block 220_k−1 is input to a first driving signal inputterminal Input1 of a k-th scan driving block 220_k, and a scan signalS[k+2] of a (K+2)nd scan driving block 220_k+2 is input to a seconddriving signal input terminal Input2. In this case, a scan start signalSSP is input to a first driving signal input terminal Input1 of thefirst scan driving block 220_1.

FIG. 7 is a timing diagram illustrating a method of driving the scandriving device of FIG. 6.

Referring to FIGS. 4, 6, and 7, the plurality of scan driving blocks220_1, 220_2, 220_3, 220_4, . . . that are included in the scan drivingdevice of FIG. 6 are formed like that of FIG. 4.

A segment t21-t22 is one segment of a reset step a and a thresholdvoltage compensation step b in which a scan signal of a gate-on voltageis simultaneously output to the plurality of scan lines S1-Sn. A drivingoperation at the segment t21-t22 is the same as a driving operation atthe segment t11-t12 that is described in FIG. 5 and therefore adescription thereof will be omitted.

Segments after a segment t23 are segments of a scan step c in which ascan signal of a gate-on voltage is sequentially output to the pluralityof scan lines S1-Sn. At segments after the segment t23, an outputcontrol signal GCK is applied as a voltage of a logic high level. At asegment in which a scan signal of a gate-on voltage is sequentiallyoutput to a plurality of scan lines S1-Sn, a clock signal that isshifted by 1 duty of a clock signal that is input to a first clocksignal input terminal CK1 of the plurality of scan driving blocks 220_1,220_2, 220_3, 220_4, . . . is input to a second clock signal inputterminal CK2.

A scan start signal SSP is applied as a voltage of a logic low level ata segment t23-t25. A voltage of a first clock signal CLK1 is repeatedlychanged to a logic low level and a logic high level in a unit of 2horizontal cycles from a segment t23-t25. A voltage of a second clocksignal CLK2 is repeatedly changed to a logic low level and a logic highlevel in a unit of 2 horizontal cycles from a segment t24-t26. A voltageof a third clock signal CLK3 is repeatedly changed to a logic low leveland a logic high level in a unit of 2 horizontal cycles from a segmentt25-t27. A voltage of a fourth clock signal CLK4 is repeatedly changedto a logic low level and a logic high level in a unit of 2 horizontalcycles from a segment t26-t28.

Thus, the second clock signal CLK2 is a signal in which the first clocksignal CLK1 is shifted by ½ duty of the first clock signal CLK1, thethird clock signal CLK3 is a signal in which the second clock signalCLK2 is shifted by ½ duty of the second clock signal CLK2, and thefourth clock signal CLK4 is a signal in which the third clock signalCLK3 is shifted by ½ duty of the third clock signal CLK3.

At the segment t23-t25, a scan start signal SSP of a logic low level isapplied to the first driving signal input terminal Input1 of the firstscan driving block 220_1, and a first clock signal CLK1 of a logic lowlevel is applied to the first clock signal input terminal CK1. A voltageof a logic low level is transferred to the first node N11, and a voltageof a logic high level is transferred to the second node N12. The secondtransistor M12 is turned on, and a voltage of a logic high level istransferred to the output terminal OUT through the turned-on secondtransistor M12. The first capacitor C11 is charged by a voltagedifference between a voltage of a logic low level of the first node N11and a voltage of a logic high level of the output terminal OUT.

At a segment t25-t27, a first clock signal CLK1 of a logic high level isapplied to the first clock signal input terminal CK1 of the first scandriving block 220_1, and a third clock signal CLK3 of a logic low levelis applied to a second clock signal input terminal CK2. The first nodeN11 and the second node N12 are in a floating state. A voltage of thesecond node N12 sustains a logic high level. A second transistor M12 isturned on by boot strap through the first capacitor C11. A voltage of alogic low level is transferred to the output terminal OUT through theturned-on second transistor M12. Accordingly, the first scan drivingblock 220_1 outputs a scan signal S[1] of a logic low level.

The second clock signal CLK2 is applied in a logic low level for asegment t24-t26, and a scan signal S[1] of a logic low level of thefirst scan driving block 220_1 is applied to a first driving signalinput terminal Input1 of the second scan driving block 220_2 for asegment t25-t27. Accordingly, the second scan driving block 220_2charges the first capacitor C11 by a voltage difference between avoltage of a logic low level of the first node N11 and a voltage of alogic high level of the output terminal OUT for a segment t25-t26.

At a segment t26-t28, a second clock signal CLK2 of a logic high levelis applied to the first clock signal input terminal CK1 of the secondscan driving block 220_2, and a fourth clock signal CLK4 of a logic lowlevel is applied to a second clock signal input terminal CK2. The secondscan driving block 220_2 outputs a scan signal S[2] of a logic low levelby operating like operation at a segment t25-t27 of the first scandriving block 220_1.

At a segment t27-t29, a third scan driving block 220_3 outputs a scansignal S[3] of a logic low level by driving with the same method as thatof the second scan driving block 220_2. A scan signal S[3] of a logiclow level of the third scan driving block 220_3 is transferred to thesecond driving signal input terminal Input2 of the first scan drivingblock 220_1. A fourth transistor M14 of the first scan driving block220_1 is turned on by the first clock signal CLK1 of a logic low level,and a seventh transistor M17 is turned on by the scan signal S[3] of thethird scan driving block 220_of a logic low level. A second power sourcevoltage VGL is transferred to the second node N12 of the first scandriving block 220_1. A first transistor M11 and an eighth transistor M18of the first scan driving block 220_1 are turned on. A voltage of alogic high level is transferred to the output terminal OUT through theturned-on first transistor M11. In this case, a first power sourcevoltage VGH is transferred to the first node N11 through the turned-oneighth transistor M18.

In this way, after a scan signal of a logic low level is output, byturning on the eighth transistor M18, the first power source voltage VGHis transferred to the first node N11, and thus a scan signal S[1] of thefirst scan driving block 220_1 may be prevented from being shaken by aclock signal that applied to the second clock signal input terminal CK2.

By the above-described method, the plurality of scan driving blocks220_1, 220_2, 220_3, 220_4, . . . shift scan signals S[1], S[2], S[3],S[4], . . . having a duty of 2 horizontal cycle by 1 horizontal cycleand sequentially output the scan signals S[1], S[2], S[3], S[4], . . . .

FIG. 8 is a block diagram illustrating a configuration of a scan drivingdevice according to another example embodiment.

In the example embodiment shown in FIG. 8, the scan driving deviceincludes a sequentially arranged plurality of scan driving blocks 230_1,230_2, 230_3, 230_4, . . . . Each of the scan driving blocks 230_1,230_2, 230_3, 230_4, . . . may be formed like the scan driving block ofFIG. 4.

A first clock signal CLK1 is input to a first clock signal inputterminal CK1 of a first scan driving block 230_1 of the plurality ofscan driving blocks 230_1, 230_2, 230_3, 230_4, . . . , and a secondclock signal CLK2 is input to a second clock signal input terminal CK2.The second clock signal CLK2 is input to a first clock signal inputterminal CK1 of the second scan driving block 230_2, and a third clocksignal CLK3 is input to the second clock signal input terminal CK2. Thethird clock signal CLK3 is input to a first clock signal input terminalCK1 of a third scan driving block 230_3, and a fourth clock signal CLK4is input to the second clock signal input terminal CK2. The fourth clocksignal CLK4 is input to a first clock signal input terminal CK1 of afourth scan driving block 230_4, and the first clock signal CLK1 isinput to the second clock signal input terminal CK2.

The second clock signal CLK2 is a signal in which the first clock signalCLK1 is shifted by ½ duty of the first clock signal CLK1, the thirdclock signal CLK3 is a signal in which the second clock signal CLK2 isshifted by ½ duty of the second clock signal CLK2, and the fourth clocksignal CLK4 is a signal in which the third clock signal CLK3 is shiftedby ½ duty of the third clock signal CLK3.

In this way, a clock signal that is shifted by ½ duty of a clock signalthat is input to the first clock signal input terminal CK1 of theplurality of scan driving blocks 230_1, 230_2, 230_3, 230_4, . . . isinput to the second clock signal input terminal CK2.

An output control signal GCK is input to an output control signal inputterminal GK of the plurality of scan driving blocks 230_1, 230_2, 230_3,230_4, . . . .

When the plurality of scan driving blocks 230_1, 230_2, 230_3, 230_4, .. . sequentially output a scan signal, a scan signal S[k−1] of a (K−1)stscan driving block 230_k−1 is input to a first driving signal inputterminal Input1 of a k-th scan driving block 230_k, and a scan signalS[k+2] of a (K+2)nd scan driving block 230_k+2 is input to a seconddriving signal input terminal Input2. In this case, a scan start signalSSP is input to the first driving signal input terminal Input1 of thefirst scan driving block 230_1.

FIG. 9 is a timing diagram illustrating a method of driving the scandriving device of FIG. 8.

Referring to FIGS. 4, 8 and 9, the plurality of scan driving blocks230_1, 230_2, 230_3, 230_4, . . . that are included in the scan drivingdevice of FIG. 8 are formed, as shown in FIG. 4. A configuration of thescan driving device of FIG. 8 different from that of the scan drivingdevice of FIG. 6 will be described.

A clock signal that is shifted by ½ duty of a clock signal that is inputto the first clock signal input terminal CK1 of the plurality of scandriving blocks 230_1, 230_2, 230_3, 230_4, . . . is input to the secondclock signal input terminal CK2. Compared with the driving method ofFIG. 7, a time period that charges the first capacitor C11 of theplurality of scan driving blocks 230_1, 230_2, 230_3, 230_4, . . . isreduced to ½, and a rising time that outputs a scan signal in a logichigh level and then outputs in a logic low level may be reduced. Thiswill be described with, for example, the first scan driving block 230_1.

For a segment t33-t34 in which a scan start signal SSP and a first clocksignal CLK1 are input in a logic low level and in which a second clocksignal CLK2 is input in a logic high level, a first capacitor C11 ischarged. At a time point t34, as the second clock signal CLK2 is inputin a logic low level, charge of the first capacitor C11 is stopped, anda scan signal S[1] of a logic low level is output. Thus, the firstcapacitor C11 is charged for 1 horizontal cycle. Compared with thedriving method of FIG. 7, a time period that charges the first capacitorC11 is reduced to ½.

At a time point t36, a scan signal S[3] of a logic low level that isoutput from a third scan driving block 230_3 is transferred to a seconddriving signal input terminal Input2 of the first scan driving block230_1, and thus a seventh transistor M17 is turned on. In this case,because the first clock signal CLK1 is applied in a logic high level, afourth transistor M14 is in a turn-off state, and a second power sourcevoltage VGL is not transferred to a second node N12. Therefore, avoltage of the first node N11 sustains a logic low level, and a secondclock signal CLK2 that is applied to a second clock signal inputterminal CK2 is continuously output. At a time point t36, a voltage ofthe second clock signal CLK2 increases to a logic high level, and thesecond clock signal CLK2 transfers a voltage of a logic high level tothe output terminal OUT.

At a time point t37, the first clock signal CLK1 is lowered to a logiclow level, and a fourth transistor M14 is turned on. The second powersource voltage VGL is transferred to the second node N12 to turn on thefirst transistor M11 and the eighth transistor M18. A voltage of a logichigh level is transferred to the output terminal OUT through theturned-on first transistor M11.

In the driving method of FIG. 7, the second transistor M12 has a sizerelatively larger than that of the first transistor M11. When a voltageof a logic high level is transferred to the first node N11 and a voltageof a logic low level is transferred to the second node N12, a timeperiod in which the second transistor M12 is turned off may be longerthan a time period in which the first transistor M11 is turned on.Further, a voltage change of a clock signal that is input to the secondclock signal input terminal CK2 may be delayed. Accordingly, when avoltage of a logic high level is transferred to the output terminal OUTthrough the first transistor M12, a voltage of a logic low level istemporarily transferred to the output terminal OUT through the secondtransistor M12, and thus a rising time in which a voltage of the outputterminal OUT increases from a logic low level to a logic high level mayincrease.

In a driving method of FIG. 9, when a scan driving block outputs a scansignal to a logic low level and then outputs to a logic high level,first transfers a voltage of a logic high level to the output terminalOUT through the turned-on second transistor M12, and then turns off thesecond transistor M12 and turns on the first transistor M11.Accordingly, a rising time in which a voltage of the output terminal OUTrises from a logic low level to a logic high level may be reduced.

FIG. 10 is a circuit diagram illustrating another example embodiment ofa scan driving block that is included in any one scan driving device ofFIGS. 3, 6, and 8.

In the example embodiment shown in FIG. 10, the scan driving blockincludes a plurality of transistors M21, M22, M23, M24, M25, M26, M27,and M28, and a plurality of capacitors C21 and C22.

The first transistor M21 includes a gate electrode that is connected toa second node N22, one electrode that is connected to an output controlsignal input terminal GCK, and another electrode that is connected to anoutput terminal OUT.

A second transistor M22 includes a gate electrode that is connected to afirst node N21, one electrode that is connected to a second clock signalinput terminal CLK2, and another electrode that is connected to theoutput terminal OUT.

A third transistor M23 includes a gate electrode that is connected tothe first clock signal input terminal CLK1, one electrode that isconnected to the first driving signal input terminal Input1, and anotherelectrode that is connected to the first node N21.

A fourth transistor M24 includes a gate electrode that is connected tothe first clock signal input terminal CLK1, one electrode that isconnected to another electrode of a seventh transistor M27, and anotherelectrode that is connected to a second node N22.

A fifth transistor M25 includes a gate electrode that is connected tothe first driving signal input terminal Input1, one electrode that isconnected to a first power source voltage VGH, and another electrodethat is connected to one electrode of a sixth transistor M26.

The sixth transistor M26 includes a gate electrode that is connected tothe first clock signal input terminal CLK1, one electrode that isconnected to the other electrode of the fifth transistor M25, andanother electrode that is connected to the second node N22.

The seventh transistor M27 includes a gate electrode that is connectedto a second driving signal input terminal Input2, one electrode that isconnected to the second driving signal input terminal Input2, andanother electrode that is connected to one electrode of the fourthtransistor M24.

An eighth transistor M28 includes a gate electrode that is connected tothe second node N22, one electrode that is connected to the first powersource voltage VGH, and another electrode that is connected to the firstnode N21.

The first capacitor C21 includes one electrode that is connected to thefirst node N21 and another electrode that is connected to the outputterminal OUT. A second capacitor C22 includes one electrode that isconnected to an output control signal input terminal GCK and anotherelectrode that is connected to the second node N22.

Compared with the scan driving block of FIG. 4, the second power sourcevoltage VGL is not connected to one electrode of the seventh transistorM27, but the second driving signal input terminal Input2 is connected toone electrode of the seventh transistor M27. Thus, by diode-connecting ascan signal (a scan signal of a (K+1)st scan driving block in FIG. 3, ora scan signal of a (K+2)nd scan driving block in FIGS. 6 and 8) that isinput to the second driving signal input terminal Input2 to the seventhtransistor M27, the second power source voltage VGL may not be used.

FIG. 11 is a circuit diagram illustrating another example embodiment ofa scan driving block that is included in any one scan driving device ofFIGS. 3, 6, and 8.

In the example embodiment shown in FIG. 11, the scan driving blockincludes a plurality of transistors M31, M32, M33, M34, M35, M36, M37,and M38 and a plurality of capacitors C31 and C32.

A first transistor M31 includes a gate electrode that is connected to asecond node N32, one electrode that is connected to an output controlsignal input terminal GCK, and another electrode that is connected to anoutput terminal OUT.

A second transistor M32 includes a gate electrode that is connected to afirst node N31, one electrode that is connected to a second clock signalinput terminal CLK2, and another electrode that is connected to theoutput terminal OUT.

A third transistor M33 includes a gate electrode connected to a firstclock signal input terminal CLK1, one electrode that is connected to afirst driving signal input terminal Input1, and another electrode thatis connected to the first node N31.

A fourth transistor M34 includes a gate electrode that is connected tothe first clock signal input terminal CLK1, one electrode that isconnected to another electrode of a seventh transistor M37, and anotherelectrode that is connected to the second node N32.

A fifth transistor M35 includes a gate electrode that is connected tothe first driving signal input terminal Input1, one electrode that isconnected to a second clock signal input terminal CLK2, and anotherelectrode that is connected to one electrode of a sixth transistor M36.

The sixth transistor M36 includes a gate electrode that is connected tothe first clock signal input terminal CLK1, one electrode that isconnected to the other electrode of the fifth transistor M35, andanother electrode that is connected to the second node N32.

The seventh transistor M37 includes a gate electrode that is connectedto a second driving signal input terminal Input2, one electrode that isconnected to a second power source voltage VGL, and another electrodethat is connected to one electrode of the fourth transistor M34.

An eighth transistor M38 includes a gate electrode that is connected tothe second node N32, one electrode that is connected to the second clocksignal input terminal CLK2, and another electrode that is connected tothe first node N31.

A first capacitor C31 includes one electrode that is connected to thefirst node N31 and another electrode that is connected to the outputterminal OUT. A second capacitor C32 includes one electrode that isconnected to the output control signal input terminal GCK and anotherelectrode that is connected to the second node N32.

Compared with the scan driving block of FIG. 4, a first power sourcevoltage VGH is not connected to one electrode of a fifth transistor M35and one electrode of an eighth transistor M38, but a second clock signalinput terminal CLK2 is connected to one electrode of a fifth transistorM35 and one electrode of an eighth transistor M38. Thus, when a clocksignal that is input to the first clock signal input terminal CLK1 is alogic low level, by using a clock signal that is applied to a logic highlevel, the first power source voltage VGH may not be used.

By way of summation and review, a scan driving device may have astructure in which a plurality of scan driving blocks are sequentiallyarranged so as to sequentially output a scan signal of a gate-onvoltage. A plurality of scan driving blocks may sequentially output ascan signal of a gate-on voltage using a method in which a subsequentscan driving block receives an output signal of a previously arrangedscan driving block to generate an output signal. In this case, aplurality of clock signals may be used for corresponding synchronizationof a plurality of scan driving blocks. A clock signal may periodicallychange to a voltage of a logic high level and a voltage of a logic lowlevel.

At a segment in which a scan signal should be applied to a voltage of aconstant level, an output signal of the scan driving device may beshaken by a clock signal in which a voltage level periodically changes.When an output signal of a previously arranged scan driving block of aplurality of scan driving blocks may be shaken by a clock signal, anoutput signal of a subsequent scan driving block that receives theoutput signal may be influenced, and accumulation of such an influencemay cause an erroneous operation of the scan driving device.

As described herein, embodiments may provide a scan driving device and amethod of driving the same that help prevent an output signal beingshaken by a clock signal. Thus, the scan driving device may prevent ascan signal from shaking according to a voltage change of a clock signaland stably output a scan signal.

While this invention has been described in connection with what ispresently considered to be practical example embodiments, it is to beunderstood that the invention is not limited to the disclosedembodiments, but, on the contrary, is intended to cover variousmodifications and equivalent arrangements included within the spirit andscope of the appended claims.

DESCRIPTION OF SYMBOLS

100: signal controller

200: scan driving device

210: scan driving block

300: data driver

500: display unit

What is claimed is:
 1. A scan driving device, comprising: a plurality ofsequentially arranged scan driving blocks, each of the plurality of scandriving blocks including: a first node to which a signal that is inputto a first driving signal input terminal is transferred according to aclock signal that is input to a first clock signal input terminal; asecond node to which a second power source voltage is transferredaccording to the clock signal that is input to the first clock signalinput terminal and a signal that is input to a second driving signalinput terminal; a first transistor including a gate electrode that isdirectly connected to the second node, a first electrode to which anoutput control signal is input, and a second electrode; a secondtransistor including a gate electrode that is connected to the firstnode, a first electrode that is connected to a second clock signal inputterminal, and a second electrode; and a third transistor including agate electrode that is directly connected to the second node, anelectrode that is connected to a first power source voltage, and anotherelectrode that is connected to the first node, wherein the secondelectrode of the first transistor and the second electrode of the secondtransistor are commonly connected at an output terminal outputting ascan signal.
 2. The scan driving device of claim 1, wherein each of theplurality of scan driving blocks further includes a fourth transistorincluding a gate electrode that is connected to the first clock signalinput terminal, an electrode that is connected to the first clock signalinput terminal, and another electrode that is connected to the firstnode.
 3. The scan driving device of claim 1, wherein each of theplurality of scan driving blocks further includes: a fifth transistorincluding a gate electrode that is connected to the first driving signalinput terminal and an electrode that is connected to the first powersource voltage; and a sixth transistor including a gate electrode thatis connected to the first clock signal input terminal, an electrode thatis connected to another electrode of the fifth transistor, and anotherelectrode that is connected to the second node.
 4. The scan drivingdevice of claim 1, wherein each of the plurality of scan driving blocksfurther includes: a seventh transistor including a gate electrode thatis connected to the second driving signal input terminal and anelectrode that is connected to the second power source voltage; and aneighth transistor including a gate electrode that is connected to thefirst clock signal input terminal, an electrode that is connected toanother electrode of the seventh transistor, and another electrode thatis connected to the second node.
 5. The scan driving device of claim 1,wherein each of the plurality of scan driving blocks further includes afirst capacitor including an electrode that is connected to the firstnode and another electrode that is connected to the output terminal. 6.The scan driving device of claim 1, wherein each of the plurality ofscan driving blocks further includes a second capacitor including anelectrode to which the output control signal is input and anotherelectrode that is connected to the second node.
 7. The scan drivingdevice of claim 1, wherein: a first clock signal is input to a firstclock signal input terminal of a plurality of first scan driving blocksof the plurality of scan driving blocks, and a second clock signal isinput to a second clock signal input terminal thereof, and the secondclock signal is input to a first clock signal input terminal of aremaining plurality of second scan driving blocks of the plurality ofscan driving blocks, and the first clock signal is input to a secondclock signal input terminal thereof.
 8. The scan driving device of claim7, wherein the second clock signal is a signal that is shifted by dutyof the first clock signal.
 9. The scan driving device of claim 8,wherein: a scan signal of a previously arranged second scan drivingblock is input to the first driving signal input terminal of asubsequently arranged first scan driving block, and a scan signal of asubsequently arranged second scan driving block is input to a seconddriving signal input terminal of a previously arranged first scandriving block.
 10. The scan driving device of claim 9, wherein: a scansignal of the previously arranged first scan driving block is input tothe first driving signal input terminal of the subsequently arrangedsecond scan driving block, and a scan signal of the subsequentlyarranged first scan driving block is input to the first driving signalinput terminal of the previously arranged second scan driving block. 11.The scan driving device of claim 1, wherein: a first clock signal isinput to a first clock signal input terminal of a first scan drivingblock of one of the plurality of scan driving blocks, and a third clocksignal that is shifted by duty of the first clock signal is input to thesecond clock signal input terminal of the first scan driving block, anda second clock signal that is shifted by ½ duty of the first clocksignal is input to a first clock signal input terminal of a second scandriving block that is arranged after the first scan driving block, and afourth clock signal that is shifted by ½ duty of the third clock signalis input to the second clock signal input terminal of the second scandriving block.
 12. The scan driving device of claim 11, wherein: a scansignal of a previously arranged scan driving block is input to the firstdriving signal input terminal of the first scan driving block, and ascan signal of a scan driving block that is arranged after the secondscan driving block is input to the second driving signal input terminalof the first scan driving block.
 13. The scan driving device of claim12, wherein a scan signal of the first scan driving block is input tothe first driving signal input terminal of the second scan drivingblock.
 14. The scan driving device of claim 1, wherein: a first clocksignal is input to a first clock signal input terminal of a first scandriving block of one of the plurality of scan driving blocks, and asecond clock signal that is shifted by ½ duty of the first clock signalis input to the second clock signal input terminal of the first scandriving block, the second clock signal is input to the first clocksignal input terminal of a second scan driving block that is arrangedafter the first scan driving block, and a third clock signal that isshifted by ½ duty of the second clock signal is input to the secondclock signal input terminal of the second scan driving block, and thethird clock signal is input to a first clock signal input terminal of athird scan driving block that is arranged after the second scan drivingblock, and a fourth clock signal that is shifted by ½ duty of the thirdclock signal is input to the second clock signal input terminal of thethird scan driving block.
 15. The scan driving device of claim 14,wherein: a scan signal of a previously arranged scan driving block isinput to the first driving signal input terminal of the first scandriving block, and a scan signal of the third scan driving block isinput to the second driving signal input terminal of the first scandriving block.
 16. The scan driving device of claim 15, wherein a scansignal of the first scan driving block is input to a first drivingsignal input terminal of the second scan driving block.
 17. A scandriving device, comprising: a first node to which a signal that is inputto a first driving signal input terminal is transferred according to aclock signal that is input to a first clock signal input terminal; asecond node to which a signal that is input to a second driving signalinput terminal is transferred according to the clock signal that isinput to the first clock signal input terminal and the signal that isinput to the second driving signal input terminal; a first transistorincluding a gate electrode that is directly connected to the secondnode, a first electrode to which an output control signal is input, anda second electrode; a second transistor including a gate electrode thatis connected to the first node, a first electrode that is connected to asecond clock signal input terminal, and a second electrode; and a thirdtransistor including a gate electrode that is directly connected to thesecond node, an electrode that is connected to a first power sourcevoltage, and another electrode that is connected to the first node,wherein the second electrode of the first transistor and the secondelectrode of the second transistor are commonly connected at an outputterminal outputting a scan signal.
 18. A scan driving device,comprising: a first node to which a signal that is input to a firstdriving signal input terminal is transferred according to a clock signalthat is input to a first clock signal input terminal; a second node towhich a second power source voltage is transferred according to theclock signal that is input to the first clock signal input terminal anda signal that is input to a second driving signal input terminal; afirst transistor including a gate electrode that is directly connectedto the second node, a first electrode to which an output control signalis input, and a second electrode; a second transistor including a gateelectrode that is connected to the first node, a first electrode that isconnected to a second clock signal input terminal, and a secondelectrode; and a third transistor including a gate electrode that isdirectly connected to the second node, an electrode that is connected tothe second clock signal input terminal, and another electrode that isconnected to the first node, wherein the second electrode of the firsttransistor and the second electrode of the second transistor arecommonly connected at an output terminal outputting a scan signal.
 19. Amethod of driving a scan driving device that includes a plurality ofscan driving blocks each including a first node, a second node, a firstclock signal input terminal receiving a first clock signal, a firsttransistor that has a gate electrode directly connected to the secondnode, a first electrode to which an output control signal is input, anda second electrode, the first transistor that transfers the outputcontrol signal to an output terminal outputting a scan signal, a secondtransistor that has a gate electrode connected to the first node, afirst electrode to which a second clock signal is input, and a secondelectrode, the second transistor that transfers the second clock signalto the output terminal, a third transistor that has a gate electrodedirectly connected to the second node, a first electrode that isconnected to a first power source voltage, and a second electrode thatis connected to the first node, the third transistor that transfers agate-off voltage to the first node, and a capacitor that is connected tothe first node and the output terminal, wherein the second electrode ofthe first transistor and the second electrode of the second transistorare commonly connected at the output terminal outputting the scansignal, the method comprising: changing a voltage of the second node bythe output control signal of a gate-on voltage; turning on the firsttransistor by a voltage change of the second node and outputting theoutput control signal of the gate-on voltage as the scan signal to theoutput terminal; and turning on the third transistor by a voltage changeof the second node and turning off the second transistor by a firstpower source voltage having the gate-off voltage.
 20. The method ofclaim 19, wherein the changing of a voltage of the second node and theoutputting of the output control signal of the gate-on voltagesimultaneously occur in the plurality of scan driving blocks.
 21. Themethod of claim 19, further comprising: applying a previous scan signalof a gate-on voltage that is output by a previously arranged scandriving block of the plurality of scan driving blocks according to thesecond clock signal to the first node; turning on the second transistorby a gate-on voltage of the first node and outputting the second clocksignal of a gate-off voltage as the scan signal to the output terminal;and charging the capacitor with a gate-on voltage of the first node anda gate-off voltage of the output terminal.
 22. The method of claim 21,wherein the second clock signal is a signal that is shifted by duty ofthe first clock signal.
 23. The method of claim 21, wherein the secondclock signal is a signal that is shifted by ½ duty of the first clocksignal.
 24. The method of claim 21, further comprising: changing thefirst clock signal to a gate-on voltage; turning on the secondtransistor by boot strap through the capacitor; and outputting thesecond clock signal of the gate-on voltage as the scan signal to theoutput terminal.
 25. The method of claim 24, further comprising:applying a gate-on voltage to the second node by the second clock signaland a scan signal of a gate-on voltage of a subsequently arranged scandriving block of the plurality of scan driving blocks; turning on thefirst transistor by a gate-on voltage of the second node and outputtingan output control signal of a gate-off voltage as the scan signal to theoutput terminal; and transferring a gate-off voltage to the first nodeby turning on the third transistor by a gate-on voltage of the secondnode and turning off the second transistor by a gate-off voltage of thefirst node.